1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a semiconductor device having multilayer interconnection, and a conductive barrier film, which are formed in a damascene structure, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
For a semiconductor device having a Cu wiring, as a technology for improving electromigration resistance, there is a well known technology, as disclosed in Japanese Patent Application Laid-open Publication No. 2006-60166, for example, in which a conductive barrier film such as cobalt tungsten phosphorous (CoWP) is formed on a Cu wiring.
A semiconductor device using a conventional conductive barrier film is described below with reference to FIG. 10.
FIG. 10 is a cross-sectional view showing a structure of a conventional semiconductor device. On an Si substrate (not shown), a first interlayer insulation film 1 having a lower wiring groove 1a is formed. In the lower wiring groove 1a of the first interlayer insulation film 1, a lower wiring 2 is formed in which a first barrier metal film 2a and a first Cu film 2b are formed. On the lower wiring 2, a conductive barrier film 3 such as CoWP is formed.
On the first interlayer insulation film 1 and the conductive barrier film 3, a second interlayer insulation film 4 is formed. In a lower portion of the second interlayer insulation film 4 and in the barrier film 3, a via hole 4a is formed so that an upper surface of the lower wiring 2 is exposed through the via hole 4a, and an upper wiring groove 4b communicated with the via hole 4a is concurrently formed on an upper portion of the second interlayer insulation film 4. In the via hole 4a and the upper wiring groove 4b, an upper wiring 6, constituted by a second barrier metal film 6a and a second Cu film 6b, is formed. The upper wiring 6 is formed in the via hole 4a and has a via 6c, constituted by the second barrier metal film 6a and the second Cu film 6b, through which the lower wiring 2 and the upper wiring 6 are electrically connected to each other.
Here, pay attention to connection parts between the vias 6c and the lower wiring 2 in FIG. 10. These connection parts do not have a conductive barrier film at an interface where a lower surface of the vias 6c and the lower wiring 2 are joined. In other words, when the via hole 4a is formed, a conductive barrier film is removed from the bottom of the via hole 4a. 
However, in a conventional technology, the following problem has been occurred.
The inventor has newly found out that a reaction layer is unnecessarily formed between a conductive barrier film such as CoWP and a lower wiring. To be more precise, in the conventional case, even if a conductive barrier film is removed from the bottom of a via hole at the time of forming the via hole while, for example, a CoWP layer or a CoWB layer as a barrier film is used, a reaction layer (Co—Cu alloy) mainly made of Co in a barrier film and Cu constituting the lower wiring remains on the surface of a lower wiring. For this reason, a high resistance reaction layer is serially inserted between a via and a lower wiring, which causes a problem that the resistance of the via cannot be sufficiently reduced.